The Asynchronous Transfer Mode (ATM) communications protocol involves organizing and transmitting data in a contiguous 53-byte cell sequence comprising a 5-byte header and a 48-byte information portion. The principal function of an ATM matrix is to transfer the entire 53 bytes as a single unit from one of the inputs to one of the outputs. However, each cell must be presented to the ATM matrix at the beginning of a specified time slot during which the matrix is available for accepting and switching the cell. Otherwise, if a cell is not aligned within the time slot, only that portion of the cell within the time slot will be switched. This cell fragmentation is clearly undesirable since the cell must remain intact when being transferred in an ATM environment.
Accordingly, as each cell arrives from an input network at arbitrary time intervals, a mechanism is needed to delay the cell by an appropriate amount so that the cell is received by the ATM matrix at a time which is coincident with a switching interval of the ATM matrix.